Past Projects
The following is a list of previous research projects in the area of
accelerators.
Streamroller: This is our framework
for automatically synthesizing systems of loop accelerators. An accelerator
system is specified by a set of C loops and an overall throughput requirement;
the design system minimizes overall hardware cost while meeting the desired
performance. The hardware cost of the accelerators is reduced by exploiting
fine-grained and coarse-grained hardware sharing.
Dynamic frequency/voltage scaling: An
accelerator datapath can be augmented with in-situ error detection and recovery
mechanisms, enabling frequency and/or voltage to be pushed beyond design-time
margins.
Coarse-grained reconfigurable architectures:
Architectures consisting of distributed meshes of function units (FUs) are able
to exploit high degrees of parallelism. Compiling code to such architectures is
challenging, because not only must the compiler schedule computation operations
on FUs, it must also route data through the mesh network.
Configurable compute accelerators: The addition
of a compute accelerator inside a processor pipeline can yield significant
speedup. The challenge is how to design the accelerator and integrate it into
the pipeline in a transparent way, i.e., so it can be utilized effectively
without changing the ISA.
Page last modified January 22, 2016.
