CCCP: Research Overview

The focus of the CCCP project is automatic synthesis of programmable application specific architectures. Application-specific architectures are hardware computing systems whose design is highly customized to an application or small set of applications. All aspects of a hardware system can be customized including the datapath, control path, instruction set, interconnect, and instruction/data memory subsystems. The basic principle of application specific design is that substantial efficiency gains are achievable when the computing platform is designed to perform a small number of tasks. These efficiency gains translate directly into the ability to scale performance, create more energy efficient designs, and reduce both cost and complexity of implementations.

Bridging the gap between ASICs and general purpose processors

The flexibility, performance, and energy consumption characteristics of embedded architectures vary widely. On one hand, general purpose designs, such as the ARM and Intel XScale series of processors, are designed for maximum flexibility, allowing a wide range of applications to map onto them. However, the performance and/or energy characteristics of general-purpose processors are often limited. Digital signal processors (DSPs) are similar to general purpose designs, though their datapaths and instruction sets are more specialized to the computation requirements of signal processing. On the other end of the spectrum, application-specific integrated circuits (ASICs) realize a specific application using efficiently designed custom logic. This yields the best performance and energy efficiency possible for a given application. However, ASIC solutions have a large drawback - loss of programmability; an ASIC solution is hardwired for one specific task. Comparing general-purpose microprocessors and ASICs, there is an efficiency gap on the order of 100-1000x in terms of computations per unit of power (MOPS/mW).

The goal of CCCP is to create hardware designs that bridge the gap between ASIC and general-purpose processor solutions. Highly specialized designs are created through ASIC-style customization techniques to capture the efficiency wins. Programmability is ensured in the design by performing customization using a compiler-orchestrated approach that ensures multiple applications can be mapped onto the generated hardware.

Our work focuses on two alternative design platforms that bridge this gap. A customized processor is a programmable processor that has been specialized for a particular application or domain of applications. By taking advantage of the characteristics of the application, large design wins are possible. A programmable loop accelerator consists of custom logic designed to accelerate specific loop nests within an application. However, this loop accelerator has the advantage of being semi-programmable so that the software may be modified after the hardware has been designed. Both of these architectures bridge the gap between general-purpose processors and ASICs by utilizing application specific design while still allowing for programmability.

CCCP System

An overview of the envisioned CCCP synthesis system is presented in the figure to the right. The system generates finely tuned customized computing solutions based on application requirements and user-controlled specifications. Inputs to the system are the application(s), performance/energy targets, and optional hardware configuration options. Output of the system is the HDL description of the customized processor or programmable loop accelerator. In addition to the hardware description, the CCCP system automatically generates the VLIW code for the processor (or microcoded instruction words for accelerators) along with fully retargeted platform development tools, including compiler, processor simulator, and customized ISA definition.

The underlying principle of the entire system is compiler-orchestrated hardware customization. Traditionally, compilers map high-level language programs onto predefined hardware platforms. To accomplish this task, they employ sophisticated analysis, optimization, scheduling and resource allocation methods. These technologies enable the compiler to understand, model, and transform applications to enable efficient mapping onto the target hardware platform. The goal of CCCP is to leverage, modify, and re-orchestrate these technologies to facilitate the design of customized computing solutions. Through sophisticated dependence, control flow, and dataflow analysis techniques, the computation and communication structure of an application can be discovered. Conventional optimizations along with hardware-centric optimizations are applied to transform the application so that it is more amenable for a customized platform. Finally, advanced instruction scheduling, modulo scheduling, and resource allocation techniques are employed to derive a highly efficient processor architecture. In essence, the compiler's job is reversed from mapping software onto a hardware platform to creating an optimized hardware from a software specification.

The CCCP project focuses on five core research areas:

Page last modified May 3, 2007.