Designing application-specific embedded systems is a very difficult task, mainly because of the large design space and the complex trade-offs involved with the various parameters. Typically, architects explore a small fraction of the overall design space, using ad-hoc techniques, and then implement a design that can be very buggy. Our research in automated synthesis develops techniques to better cover the design space, and to automatically create chips that are correct by construction. A figure representing our system is displayed below.
System Overview
The over-arching strategy employed by the synthesis system is to hierarchically explore the vast design space. To this end, we are developing a design system which specifies top level parameters first and progressively fills in the details.
- SpaceWalker: Design parameters that are difficult to analytically determine are heuristically explored via the spacewalker. "Analytically determined" means that by simply examining the application, appropriate decisions can be made about the resulting architecture; no exploration of the design space is necessary. Currently, we envision the space walker providing high-level parameters of an architecture, such as the number of clusters or the number of function units needed to sustain performance. Since these numbers can vary widely based on target performance and cost goals, the design space cannot be analytically determined. The spacewalker receives cost estimates from the synthesis system and performance estimates from the retargetable compiler in order to guide the exploration process.
- Hardware Compiler: Low-level parameters, which can be analytically determined (e.g. instruction set extensions), are specified by the hardware compiler. The hardware compiler takes a set of high-level parameters determined by the spacewalker, combines that with analytically determined parameters, and produces an architectural specification used for synthesis.
- Architecture Synthesizer: The job of the architecture synthesizer is to take an architecture specification and to create HDL, such as Verilog. This involves many complicated tasks, such as high level technology mapping, where we select the appropriate implementation for functional blocks that are specified in the architecture description. HDL can be used to generate gate counts and rough power consumption estimations, used to guide the spacewalker. The architecture synthesizer also produces a machine description (MDES in the diagram), which is used to retarget our compiler.
- Retargetable Compiler: Our retargetable compiler is responsible for generating code for the customized architecture. Customizing architectures creates challenging problems for compilers, and many techniques are developed to generate quality assembly code. More detailed information on the compiler can be found here. In the context of the synthesis system, the main use of the compiler is to provide performance feedback to the spacewalker.
Page last modified January 22, 2016.