The architecture design framework is an important part of the architecture synthesis system. In the figure below, the components in the blue box make up the architecture design framework. The hardware compiler generates a high level architecture specification (or archspec) based on the application and a parallelism specification. From this archspec, various phases of architecture synthesis must be performed which will accomplish the following tasks:
- Generate a low level architecture description with detailed information about the implementation of functionality and connectivity within the architecture.
- Estimate the hardware cost of the architecture, which will be fed back to the spacewalker.
- Generate HDL for the architecture.
- Generate a machine description which will be used by the retargetable compiler to compile the application for the architecture.
- Generate an architecture simulator to verify the design and provide performance and power estimates.
Key to the architecture design framework is the internal description of the architecture. In general, an architecture description can specify a processor using various levels of abstraction. A higher level description is easier to write or generate, which is an important feature when architectures are being created in a design space exploration system. Leaving too many details to be explored means that the design space will be large and a good design may not be easily found. On the other hand, a lower level description allows more flexibility, as more details of the processor can be specified.
In our system, a multi-level architecture description is used. This gives the advantages of both high and low level representations. A high level representation (labeled HL in the above figure) is generated from the hardware compiler's archspec. This representation is then lowered during the Architecture Synthesis phase of the design framework, and cost estimates and HDL are generated from the low level representation (labeled LL).
The high level description contains both structural and behavioral information, as shown in the figure below. Structural information includes items such as the number and types of function units, register files, and memories, bitwidth information, and high level connectivity information. This structural information can be seen as a hardware block diagram. For example, the figure shows a 2-cluster machine with two function units and a register file in each cluster. In addition to this structural block diagram, the high level description also contains behavioral information, which describes the processor ISA including the semantics and input-output formats of the supported operations.
High Level Architecture Description
The low level description fills in the details of the processor. Connections between processor components are fully defined in terms of the specific ports, wires and buses used. Pipeline latches, multiplexers, and tristate buffers are inserted, and macrocells are selected to implement the function units. The behavioral specification is augmented with timing information.
Low Level Architecture Description
A feature of the architecture description system is that incomplete specifications are supported. Default versions of processor components and connectivity can be intelligently generated. This allows an architecture to be synthesized without having to fully specify the machine, a useful feature for research purposes. In the figure below, given three register files (general purpose, predicate, and floating point) and two function units (integer and float), along with the ISA information, a default set of connections between register files and function units can be made.
Incomplete Architecture Specification
To generate cost estimates and HDL for a given architecture, a hardware library (labeled HWLib in the system flow diagram above) is used. This library contains parameterized area, power, and delay estimates for the components in the processor, including the register files, function units, and multiplexers. From the low level architecture description and this hardware library, a cost estimate can be obtained for the processor. The hardware library also contains a structural verilog implementation for each of the architecture components. By using these components as building blocks, synthesizable HDL can be generated for the entire processor.
Generation of a compiler-oriented machine description consists of extracting resources, resource usage patterns, and physical input-output formats from the architecture description. The compiler will use the resources to model the concurrency available in the machine; thus, resources are components such as function units, register file ports, and buses. These resources and their usage patterns are obtained from the architecture description. Input-output formats are determined from the connections between function units and register files in the machine.
The architecture design framework is a collection of tools built around a multi-level architecture description system and a hardware library. Given certain high level parameters as input from a design space explorer, this framework provides the means to effectively describe, synthesize, and evaluate a candidate architecture design.
Relevant Publications
- None.
Page last modified January 22, 2016.