Current generation microprocessors employ a multitude of features to exploit ever increasing levels of performance with high efficiency. This include employing a large number of functional units to exploit ILP, clustered datapaths to provide highly scalable designs, specialized functional units to execute custom instructions, SIMD units to handle data parallelism, and support for multiple threads to exploit task level parallelism. Storage structures like special purpose register files, local memories, and stream buffers are distributed through out the data path to provide low latency high bandwidth data access. Moreover, to reduce the complexity, customized connectivity is provided between the storage structures and the functional units.
To handle such complex architectures, compilers are required which can extract the required levels of parallelism from the program and orchestrate the code so as to efficiently use the underlying hardware. The importance of a compiler is accentuated in an automated processor design system like CCCP. In order to explore a large space of architectures for an application, retargetable compilers are required which can be tuned with minimum effort to generate code to evaluate the target architecture.
Below is a list of the research work we have been doing in the area of compilers.
- Partitioning for Multicluster Architectures : Multicluster processors decentralize the datapath and register file into multiple smaller clusters in order to increase scalability. We have developed new compiler algorithms to divide both the operations in the code and the data across the partitioned processing elements.
- Power-aware Compilation : Power is a critical component in the design of embedded processors. Some of the architectural features to improve power include windowed register file architectures, low power loop caches etc. We have developed compiler algorithms to handle these features.
- Automatic Thread Extraction : Hongtao and Steve do stuff together.
- Trimaran Compiler Framework : The Trimaran compilation system forms the basis of all our current research. We have extended the Trimaran system with new capabilities like clustering, codegen, support for partial bypass, retargetable custom instruction set support etc. In addition, based on a machine description file (MDES) we have also retargeted Trimaran to the ARM and the WIMS processors.
Page last modified January 22, 2016.