- Composite Cores: is an architecture that allows reduced switching overheads between heterogenous cores by bringing the notion of heterogeneity within a single core. This architecture saves energy by enabling fine-grained switching between a high performance out-of-order pipeline and an energy efficient in-order pipeline.
- BERET: BERET is an energy efficient coprocessor that targets general purpose programs while also offering the flexibility to work across applications. It relies on recurring instruction traces to cut down on redundant instruction fetch and decode energy, and a bundled exection model to reduce register reads and writes for temporary variables.
- Polymorphic Pipeline Array: Polymorphic pipeline arrays (PPAs) are flexible media accelerators which can accelerate the code in multiple ways. Coarse-grain pipeline parallelism is exploited by concurrently executing filters in streaming applications, as well as fine-grain instruction level parallelism is also found by modulo scheduling innermost loops. It consists of an array of simple processing elements (PEs) that are tightly interconnected by a scalar operand network and a shared memory. These cores can execute tasks independently or neighboring cores can be coalesced to execute loops with high degrees of fine-grain parallelism.
- Past Projects: a list of previous research projects in the area of accelerators.
Page last modified January 22, 2016.