The Trimaran compiler framework is a retargetable compilation/simulation system that was originally designed to target a family of EPIC-style architectures based on the HPL-Playdoh ISA. We have retargeted Trimaran to the WIMS and the ARM processors. The Trimaran system consists of 3-basic components - Impact, Elcor, and Simu.
Trimaran Overall Flow
- Impact : The Impact frontend takes in the C program, performs function inlining, control-flow profiling, memory dependence analysis, classical optimizations, region formation, if-conversion etc. to generate the REBEL intermediate code.
- Elcor : The Elcor backend, based on a description of the target architecture (MDES) performs bitwidth analysis, clustering, codegen, scheduling, and register allocation to generate a machine specific REBEL code.
- MDES : The MDES is a machine description database which specifies compiler specific information of the target architecture. The MDES contains descriptions about the operations in the target-ISA, register files, resources, connectivity between the operations, register files and the resources. It also contains reservation tables and latency information used in scheduling.
- Simu : Simu is a compiled code simulator which simulates and verifies the final REBEL code.
For more information about Trimaran, please visit the Trimaran Web Site
Page last modified January 22, 2016.