A critical part of the CCCP project is manually creating prototype custom designs for a variety of applications. While automation of the process is the final goal, new application areas have different processing demands and constraints that can only be dealt with by a human designer. Our approach is to investigate these areas from the application side, characterizing and developing a comprehensive understanding of the application. New processing and memory substructures are identified or developed to facilitate efficient processing for the target applications. The overriding objective is to define a parameterized programmable architecture for the application area that can meet performance, power and cost goals.
We are currently investigating two domains: wireless protocols and speech recognition. Both of these areas provide tough challenges for designers. In the wireless area, new protocols have huge processing demands to meet the desired bandwidth constraints. Heterogeneous multiprocessor/ASIC solutions are standard in this domain. For the speech area, the goal is to create a portable solution to facilitate the use of speech recognition in mobile devices. The challenge is again performance but under very tight power constraints.
Software Defined Radio
The operation throughput requirements of current third generation (3G) wireless protocols are already an order of magnitude higher than the capabilities of modern DSP processors, a gap that is likely to grow in the future. Figure to the right shows the computation and power demands of a typical 3G wireless protocol. A comparison of the theoretical peak performance throughput and power consumption of SODA with other existing DSP, media, and general-purpose processor systems is also illustrated. While most DSP processors operate at around 10 Mops/mW, the typical wireless protocol requires 100 Mops/mW. This is the reason most wireless protocols to date have been implemented with custom hardware. While custom hardware can meet the operational requirements, a programmable solution offers many potential advantages: including multi-mode operations, faster time-to-market, rapid prototyping and bug fixes and cheaper hardware.
Speech Recognition
Speech recognition is characterized by a large number of independent threads and
a poor memory performance, owing to the large overall footprint of the speech
knowledge base and the highly input-dependent nature of the search process. These
characteristics make modern processor architectures relatively unsuitable for running
speech recognition, particularly on mobile computing platforms. The graph to the
right illustrates this point by comparing the achieved throughput of the CMU Sphinx II
speech recognition system of 5 processor platforms: ARM SA-1110, Intel Xscale, and three variants
of the Intel Pentium III. The bars plot the achieved throughput in terms of sustained
words-per-minute processing. For reference, human speech generally ranges from 150
words-per-minute for casual conversations to 250 words-per-minute for excited speech.
On top of each bar is the time duration that each processor can sustain the achieved
level of processing on 1 AA battery. The durations range from 6 hours for the ARM to
6 minutes for the 1Ghz Pentium III. While the Pentium processors can achieve real-time
performance, they are not usable in a portable environment. Conversely, the ARM system has
reasonable energy characteristics, but the performance is an order of magnitude slow.
Our objective is to define a speech recognition platform that can sustain real-time
speech processing and be usable in a mobile environment.
Page last modified January 24, 2007.