Call for Extended Abstracts

4th Workshop on Parallel Execution of Sequential Programs
on Multi-core Architectures (PESPMA 2011)
June 5, 2011 San Jose, California
In conjunction with the 38th International Symposia on Computer Architecture (ISCA)




Wei Liu

Intel Corporation


Scott Mahlke

University of Michigan


Tin-fook Ngai

Intel Labs


Program Committee


David Albonesi
Cornell University


David August

Princeton University


Koen De Bosschere

Ghent University


Calin Cascaval

Qualcomm Research


Albert Cohen

INRIA Saclay


Carol Eidt



Xiaobing Feng

Institute of Computing Technology, China


Rajiv Gupta

University of California Riverside


Robert Hundt



Manjunath Kudlur

NVIDIA Corporation


Satish Narayanasamy

University of Michigan


Rodric Rabbah

IBM Research


Youfeng Wu

Intel Labs


James Tuck

North Carolina State University

Overview and Topics


Multi-core architectures have started a new era of computing and boost performance and efficiency of parallel programs, however most of existing application base is still composed of sequential applications. How to execute those sequential programs efficiently and reliably on multi-core is remaining a critical and challenge problem. Multi-core architectures usually have many weaker cores compared to a monolithic out-of-order core, however, the aggregation of many small cores provides better computing and power efficiency than the monolithic one. To fully leverage this multi-core opportunity, a set of new tools, compiler optimizations, micro-architecture mechanisms and programming models is expected.


In this workshop, we focus on leveraging the computing power provided by multi-core to address the issues of performance, power, programming model and reliability etc. for sequential programs which are executed on homogenous or heterogeneous multi-core. The topics of particular interest include, but no limited to:


         Speculative program execution (e.g. speculative multithreading, speculative vectorization, speculative optimizations)

         Deterministically execute sequential programs in parallel

         Deterministic multi-core execution versus parallel execution of sequential programs

         Helper threading techniques (e.g. prefetch helper, verification helper)

         Automatic/semi-automatic/manual parallelization/vectorization techniques

         Reliability improvement on multi-core for sequential programs

         Power/thermal optimizations on multi-core for sequential programs

         Compiler optimizations and transformations to help single thread execution

         Binary translation/optimization to help single thread execution

         Evaluation of performance, power/thermal and reliability of sequential programs on multi-core (v.s., monolithic core)

         Trade-offs between speculation and non-speculation techniques

         Frameworks and tools for sequential execution model aimed for homogenous or heterogeneous multi-core

         Micro-architecture support for sequential program execution on multi-core

         Novel sequential programming models and support


The workshop also aims at providing a forum for researchers and engineers from academia and industry to discuss their latest research in computer architecture, compiler, programming language on sequential program execution on multi-core. Moreover, it will bring more attention of their ideas, research problems and new proposals and obtain valuable and instant feedback from fellow researchers.


Key Dates


Apr 11, 2011: Submission deadline

Apr 29, 2011: Acceptance Notification

May 09, 2011: Final version ready


Submission guidelines

Submissions should be extended abstracts or position papers of 3-5 pages, double-column, in 11-point font. Include the list of authors and their affiliations, email addresses and the name of the corresponding author. For submission instructions, see the above website.


Call for papers in pdf format.