2011 Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures
San Jose, California, June 5, 2011, in conjunction with 38th Intl. Symposium on Computer Architecture


Workshop Overview

Multi-core architectures have started a new era of computing and boost performance and efficiency of parallel programs, however most of existing application base is still composed of sequential applications. How to execute those sequential programs efficiently and reliably on multi-core is remaining a critical and challenge problem. Multi-core architectures usually have many weaker cores compared to a monolithic out-of-order core, however, the aggregation of many small cores provides better computing and power efficiency than the monolithic one. To fully leverage this multi-core opportunity, a set of new tools, compiler optimizations, micro-architecture mechanisms and programming models is expected.

In this workshop, we focus on leveraging the computing power provided by multi-core to address the issues of performance, power, programming model and reliability etc. for sequential programs which are executed on homogenous or heterogeneous multi-core. The topics of particular interest include, but no limited to:

The workshop also aims at providing a forum for researchers and engineers from academia and industry to discuss their latest research in computer architecture, compiler, programming language on sequential program execution on multi-core. Moreover, it will bring more attention of their ideas, research problems and new proposals and obtain valuable and instant feedback from fellow researchers.