Research Overview
  1. Hardware: Processors

    These are processors that have been specialized for a particular application or domain of applications. By taking advantage of the characteristics of the application, large performance and energy gains are possible, while still maintaining the flexibility of running many other applications. The customization techniques used target an entire application as opposed to programmable accelerators. In current projects we focus on the design of energy-efficient architectures for throughput oriented graphic and scientific workloads. More.
  2. Hardware: Accelerators

    Distinct from customized processors, hardware accelerators are designed to exploit characteristics of specific code structures (e.g. loops) or instruction sequences that could be found in a wide variety of domains of applications. Their role, in general, is that of co-processors that help the main general processor execute applications faster or consume less energy. Presently, we are working on an energy efficient co-processor which relies on recurring instruction traces and the design of polymorphic pipeline arrays (PPAs) targetting performance improvement of media applications. More.
  3. Runtime

    Runtime systems have the capability of observing the system during execution, enabling them to find hot sections of code or changing patterns in program execution that can potentially greatly benefit from optimizations. Unlike compiler techniques, they typically do not involve any program source code modifications. Currently we focus on enhancing the performance of multi-threaded applications through dynamic thread-level parallelism and improving the performance and energy-efficiency of mobile applications. More.
  4. Compilers

    To exploit the complex architectures prevelant today, compilers are required which can extract the required levels of parallelism from the program and orchestrate the code so as to efficiently use the underlying hardware. Other than high performance, we design compilation techniques to provide energy efficiency and better programmability. Current projects include source-to-source compilation of stream programs to CUDA for execution on GPUs and designing compiler techniques to analyze multi-threaded programs to detect and avoid concurrency bugs. More.
  5. Reliability

    As transistors shrink in size with aggressive technology scaling, they become more and more susceptible to soft errors. We work on developing minimally invasive software solutions that provide high soft error coverage with very little overhead by focussing our efforts on protecting statistically-vulnerable portions of program code. Another class of faults is hard errors which are permanent failures of devices. We provide hardware solutions to provide maximal working systems in the presence of hard errors. More.

The CCCP group works on multiple layers of the system stack. In hardware we work on designing energy-efficient architectures for throughput computing and hardware accelerators speeding up hot code regions (e.g. loops). Runtime systems implement dynamic thread-level parallelism for better performance for desktop and server applications. Also, energy-efficiency and improved performance for mobile applications is provided through runtime systems. Moving higher up in the system stack, we design compiler techniques to detect and avoid concurrency bugs in multi-threaded applications. We have designed solutions for source-to-source compilation of stream programs for execution on GPUs. Reliability of systems is a major concern even in commodity systems. We work on hardware and compiler techniques providing reliability against hard errors and soft errors. In summary, the CCCP group focusses on solutions providing better performance, energy-efficiency, reliability and programmability of applications and the system.

Page last modified April 10, 2012.